1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having fuse elements and a manufacturing method thereof.
2. Description of the Related Art
Voltage regulators and voltage detectors each include an analog processing circuit, a logic circuit, a capacitor, a bleeder resistor, and the like. In a part of the bleeder resistor, fuse elements are formed and disposed for selecting resistors to obtain a desired voltage by adjustment in an inspection step.
FIG. 5 and FIG. 6 illustrate a conventional example of a semiconductor integrated circuit having such a structure. FIG. 5 is a top view of the fuse elements, and FIG. 6 is a sectional view taken along the line A-A of FIG. 5. As illustrated in FIG. 6, the fuse elements are formed on an element isolation insulating film 401 with the same conductive material as a gate electrode of a MOSFET, in other words, by polycide films 402 (corresponding to reference numeral 302 of FIG. 5) formed of a polycrystalline Si film and a WSix film doped with impurities.
The polycide films 402 are covered with an interlayer insulating film 403 and a BPSG film 404, which being a flattering film. Contact holes 405 (corresponding to reference numeral 305 of FIG. 5) reaching to vicinities of both end portions of the polycide films 402 are opened within the BPSG film 404 and the interlayer insulating film 403. On the BPSG film 404, interconnects formed of an aluminum film 406 (corresponding to reference numeral 306 of FIG. 5) of a first layer are patterned so that the interconnects are brought into contact with the polycide films 402 through the contact hole 405. The aluminum films 406 are covered with a metal interlayer insulating film 407 of a first layer made from TEOS as a raw material by plasma CVD.
Although not illustrated, in the above-mentioned conventional example, an aluminum film of a second layer is also used in addition to the aluminum film of the first layer. Accordingly, as a flattening film between those aluminum films, an SOG film 408 is formed on the metal interlayer insulating film 407 of the first layer by rotation coating, curing, and etch-back thereafter. The SOG film 408 are covered with the metal interlayer insulating film 409 of the second layer, which is made from TEOS as a raw material by plasma CVD. The metal interlayer insulating film 409 of the second layer is covered with an SiN film 410, which is an overcoat film formed by plasma CVD.
Besides, opening regions 311 are formed on the polycide films 402 for cutting the polycide films 402, which are the fuse elements, with a laser beam. The opening regions 311 are formed by etching using the same mask used for etching the SiN film 410 on an aluminum pad (not shown) at the same time. However, due to over etching, the opening regions 311 reach to the metal interlayer insulating film 409 of the second layer.
Japanese Patent Application Laid-open No. 05-021695 suggests, in addition to such structure described above, a structure, by which cracks or peeling of an SiN film, or the like may be prevented from occurring.
Further, Japanese Patent Application Laid-open No. 07-022508 suggests a structure in which a guard ring layer is provided at surroundings of the fuse elements, whereby entry of a foreign matter or water may be prevented.
In the voltage regulators and the voltage detectors, an operation test is conducted in a wafer state after the formation of the elements, and simultaneously corresponding fuse element of the resistor is cut to obtain a desired voltage.
In this regard, as is apparent from FIG. 5 and FIG. 6, the SOG films 408 are exposed to inner side surfaces of the opening regions 311 for trimming processing of the fuse elements, in particular, between the aluminum interconnects connected to the adjacent fuse elements. However, each of the SOG films 408 has such a nature as being likely to absorb water. For that reason, water or moisture entered from an outside is contaminated into internal elements of the semiconductor integrated circuit through the SOG film 408, resulting in a cause of a reliability failure of a semiconductor integrated circuit device.